module shifter (
  ld, clk, en, q
);

  input ld, clk, en;
  output[51:0] q;
  reg[51:0] q;

  always @(posedge clk) begin
    if ( ld ) q = 52'haaa3190102201;
    else if ( en ) q = {q[47:0], q[51:48]};
  end


endmodule